RTU Computer Architecture and Organization Model Question Papers of 6 Semester for Computer Science Engineering 2020
Paper Code: 6CS4-04
Subject: Computer Architecture and Organization
Branch: Computer Science
Prepared By: Ms. Dimple Jayaswal (Assistant Professor, GIT Jaipur)
RTU Computer Architecture Exam Paper - CA Model Paper 2020
- Draw Von Neumann Architecture with the diagram.
- Define Cache Memory.
- How a virtual address does get translated into a physical address?
- What is Segmentation?
- What is Paging?
- Draw and define the Priority encoder.
- Explain the Flynn Classification.
- Design the basic computer and define computer architecture, computer organization.
- Design a 4 bit by 3 bit array multiplier.
- What is DMA?
1.) Design one stage of arithmetic logic unit circuit that includes:-
a) 4-bit Adder and
c) 4-bit Logic Unit
2.) Describe the Bus and Memory transfer.
3.) Write all possible addressing modes; also explain each by taking an appropriate numerical example?
4.) Differentiate RISC & CISC architecture.
5.) Explain the PUSH and POP operation in stack organization.
6.) Explain the general register organization.
7.) Explain the different instruction formats in the architecture?
8.) Explain the Floating point representation.
9.) What is Associative Memory? How does is facilitate Searching? Explain?
10.) i) How many 128*8 RAM chips & 512*8 ROM Chips are needed to provide memory capacity of 2048 bytes?
ii) How many lines of the address bus must be used to access 2048 bytes of memory? How many of these lines will be common to all chips?
iii) How many lines must be decoded for chip select? Specify the size of the decoders.
iv) List the memory address map.
11.) Write all possible addressing modes; also explain each by taking an appropriate numerical example?
12.) A digital computer has a memory unit of 64k * 16 and a cache memory of 1k words. The cache uses direct mapping with a block size of 4 words.
i) How many bits are there in the tag, index, block & words fields of the address formats.
ii) How many bits are there in each word of cache?
iii) How many blocks can the cache accommodate?
13.) Explain the following in Asynchronous data transfer:
i) Strobe control
14.) Explain Direct Memory Access (DMA) Controller and Transfer in detail.
RTU Computer Architecture PART C
1.) Explain the following in Asynchronous data transfer:
(i) Strobe control (ii) Handshaking
2.) Explain four segments Instruction Pipeline with the help of space time diagram. What are the difficulties in instruction pipeline & how to handle branch instructions in pipeline?
3.) Draw and explain the hardware for Booth Algorithm, its flow chart for 2’s complement number multiplication. Multiply 0111 & 0011 with the help of Booth’s algorithm.
4.) Draw and explain the hardware for signed magnitude addition and subtraction operation, its flow chart for signed magnitude number addition and subtraction. Add 11111 & 1111. Also show
(-A)-(-B) operation results, when A>B, A=B, A<B
5.) Define Direct Memory Access? Explain Direct Memory Access (DMA) Controller and Transfer in detail.
6.) Explain the division restoring and non-storing techniques.
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